Design of Digital to Analog Voice Data Packet Conversion from Ethernet Protocol using FPGA
Abstract: This paper describes
a system that is designed to be able to receive packet voice signal using the Ethernet
protocol in local networks using FPGA which was programmed decode the data
packets. The digital data packets are then converted back into analog data that
will be used to control another system. The design was implemented as four
components consisting of frame starter unit, address matching unit, buffer unit
and DAC processing unit. The system was designed on Xilinx development board
using ISEdesign suite and simulated on ISIM. The test results showed that the
system response was less than 40 ms. The result also showed that our proposed
design only occupies 11% of number of slices and it also requires 5% of total
IOBs on Xilinx Spartan 3-E.
Author: Barlian Henryranu
Prasetio
Journal Code: jptkomputergg170106
